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4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 1 en29f800 rev. e, issue date: 2001/07/05 features 5.0v 10%, single power supply operation - minimizes system level power requirements manufactured on 0.32 m process technology high performance - access times as fast as 45 ns low power consumption - 25 ma typical active read current - 30 ma typical program/erase current - 1 a typical standby current (standard access time to active mode) flexible sector architecture: - one 16 kbyte, two 8 kbyte, one 32 kbyte, and fifteen 64 kbyte sectors (byte mode) - one 8 kword, two 4 kword, one 16 kword and fifteen 32 kword sectors (word mode) - supports full chip erase - individual sector erase supported - sector protection: hardware locking of sectors to prevent program or erase operations within individual sectors additionally, temporary sector group unprotect allows code changes in previously locked sectors. high performance program/erase speed - byte program time: 10s typical - sector erase time: 500ms typical - chip erase time: 3.5s typical low standby current - 1a cmos standby current-typical - 1ma ttl standby current low power active current - 30ma active read current - 30ma program/erase current jedec standard program and erase commands jedec standard data polling and toggle bits feature single sector and chip erase sector unprotect mode embedded erase and program algorithms erase suspend / resume modes: read and program another sector during erase suspend mode 0.32 m double-metal double-poly triple-well cmos flash technology low vcc write inhibit < 3.2v >100k program/erase endurance cycle 48-pin tsop (type 1) commercial temperature range general description the en29f800 is a 8-megabit, electrically erasable, read/write non-volatile flash memory, organized as 1,048,576 bytes or 524,288 words. any byte can be programmed typically in 10s. the en29f800 features 5.0v voltage read and write operation, with access times as fast as 45ns to eliminate the need for wait states in high-performance microprocessor systems. the en29f800 has separate output enable ( oe ), chip enable ( ce ), and write enable (we) controls, which eliminate bus contention issues. this device is designed to allow either single (or multiple) sector or full chip erase operation, where each sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. the device can sustain a minimum of 100k program/erase cycles on each sector. en29f800 8 megabit (1024k x 8-bit / 512k x 16-bit) flash memory boot sector flash memory, cmos 5.0 volt-only
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 2 en29f800 rev. e, issue date: 2001/07/05 connection diagrams table 1. pin description figure 1. logic diagram pin name function a0-a19 addresses dq0-dq14 15 data inputs/outputs dq15 / a-1 dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce chip enable oe output enable hardware reset pin ready/busy output we write enable vcc supply voltage (5v 10% ) vss ground nc internally connected pin en29f800 16 or 8 dq0 C dq15 (a-1) a0 - a18 19 we ce oe ry/by reset byte reset ry/by 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 standard tsop a15 a14 a13 a12 a11 a10 a9 a8 nc nc we# reset# nc nc ry/by# 18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte# vss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# vss ce# a0
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 3 en29f800 rev. e, issue date: 2001/07/05 table 2a. top boot block sector architecture address range sect or (x16) (x8) sector size (kbytes / kwords) a18 a17 a16 a15 a14 a13 a12 18 7e000h-7ffffh fc000h-fffffh 16/8 1 1 1 1 1 1 x 17 7d000h-7dfffh fa000h-fbfffh 8/4 1 1 1 1 1 0 1 16 7c000h-7cfffh f8000h-f9fffh 8/4 1 1 1 1 1 0 0 15 78000h-7bfffh f0000h C f7fffh 32/16 1 1 1 1 0 x x 14 70000h-77fffh e0000h - effffh 64/32 1 1 1 0 x x x 13 68000h-6ffffh d0000h - dffffh 64/32 1 1 0 1 x x x 12 60000h-6ffffh c0000h - cffffh 64/32 1 1 0 0 x x x 11 58000h-5ffffh b0000h - bffffh 64/32 1 0 1 1 x x x 10 50000h-57fffh a0000h - affffh 64/32 1 0 1 0 x x x 9 48000h-4ffffh 90000h - 9ffffh 64/32 1 0 0 1 x x x 8 40000h-47fffh 80000h - 8ffffh 64/32 1 0 0 0 x x x 7 38000h-3ffffh 70000h - 7ffffh 64/32 0 1 1 1 x x x 6 30000h-37fffh 60000h - 6ffffh 64/32 0 1 1 0 x x x 5 28000h-2ffffh 50000h C 5ffffh 64/32 0 1 0 1 x x x 4 20000h-27fffh 40000h C 4ffffh 64/32 0 1 0 0 x x x 3 18000h-1ffffh 30000h C 3ffffh 64/32 0 0 1 1 x x x 2 10000h-17fffh 20000h - 2ffffh 64/32 0 0 1 0 x x x 1 08000h-0ffffh 10000h - 1ffffh 64/32 0 0 0 1 x x x 0 00000h-07fffh 00000h - 0ffffh 64/32 0 0 0 0 x x x
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 4 en29f800 rev. e, issue date: 2001/07/05 table 2b. bottom boot block sector architecture address range sect or (x16) (x8) sector size (kbytes/ kwords) a18 a17 a16 a15 a14 a13 a12 18 78000h-7ffffh f0000h C fffffh 64/32 1 1 1 1 x x x 17 70000h-77fffh e0000h C effffh 64/32 1 1 1 0 x x x 16 68000h-6ffffh d0000h C dffffh 64/32 1 1 0 1 x x x 15 60000h-67fffh c0000h C cffffh 64/32 1 1 0 0 x x x 14 58000h-5ffffh b0000h - bffffh 64/32 1 0 1 1 x x x 13 50000h-57fffh a0000h - affffh 64/32 1 0 1 0 x x x 12 48000h-4ffffh 90000h C 9ffffh 64/32 1 0 0 1 x x x 11 40000h-47fffh 80000h C 8ffffh 64/32 1 0 0 0 x x x 10 38000h-3ffffh 70000h C7ffffh 64/32 0 1 1 1 x x x 9 30000h-37fffh 60000h C 6ffffh 64/32 0 1 1 0 x x x 8 28000h-2ffffh 50000h C 5ffffh 64/32 0 1 0 1 x x x 7 20000h-27fffh 40000h C 4ffffh 64/32 0 1 0 0 x x x 6 18000h-1ffffh 30000h C 3ffffh 64/32 0 0 1 1 x x x 5 10000h-17fffh 20000h C 2ffffh 64/32 0 0 1 0 x x x 4 08000h-0ffffh 10000h C 1ffffh 64/32 0 0 0 1 x x x 3 04000h-07fffh 08000h C 0ffffh 32/16 0 0 0 0 1 x x 2 03000h-03fffh 06000h C 07fffh 8/4 0 0 0 0 0 1 1 1 02000h-02fffh 04000h C 05fffh 8/4 0 0 0 0 0 1 0 0 00000h-01fffh 00000h C 01fffh 16/8 0 0 0 0 0 0 x
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 5 en29f800 rev. e, issue date: 2001/07/05 product selector guide product number en29f800 speed option vcc=5.0v 10% -45 -55 -70 -90 max access time, ns (t acc ) 45 55 70 90 max ce# access, ns (t ce ) 45 55 70 90 max oe# access, ns (t oe ) 25 30 30 35 block diagram we ce oe state control command register erase voltage generator input/output buffers program voltage generator chip enable output enable logic data latch y-decoder x-decoder y-gating cell matrix timer vcc detector a0-a18 vcc vss dq0-dq15 (a-1) address latch block protect switches stb stb ry/by
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 6 en29f800 rev. e, issue date: 2001/07/05 table 3. operating modes 8m flash user mode table dq8-dq15 operation ce# oe# we # reset# a0- a18 dq0-dq7 byte# = v ih byte# = v il read l l h h a in d out d out high-z write l h l h a in d in d in high-z cmos standby v cc 0.5v x x v cc 0.5v x high-z high-z high-z ttl standby h x x h x high-z high-z high-z output disable l h h h x high-z high-z high-z hardware reset x x x l x high-z high-z high-z temporary sector unprotect x x x v id a in d in d in x notes: l=logic low= v il , h=logic high= v ih , v id =11.0 0.5v, x=dont care, d in =data in, d out =data out, a in =address in table 4. device identifiction 8m flash manufacturer/device id table note: 1. if a manufacturing id is read with a8=l, the chip will output a configuration code 7fh. a further manufacturing id must be read with a8=h. 2. if a device id is read with a8=l, the chip will output configuration code 7fh. a further device id must be read with a8=h. description mode a18 to a12 a11 to a10 a9 a8 a7 a6 a5 to a2 a1 a0 dq8 to dq15 dq7 to dq0 manufacturer id: eon l l h x x v id h 1 x l x l l x 1ch word l l h 22h 89h device id (top boot block) byte l l h x x v id h 1 x l x l h x 89h word l l h 22h 8ah device id (bottom boot block) byte l l h x x v id h 1 x l x l h x 8ah x 01h (unprotected) sector protection verification l l h sa x v id h 1 x l x h l x 00h (protected) oe ce we
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 7 en29f800 rev. e, issue date: 2001/07/05 user mode definitions word / byte configuration the signal set on the byte# pin controls whether the device data i/o pins dq15-dq0 operate in the byte or word configuration. when the byte# pin is set at logic 1, then the device is in word configuration, dq15-dq0 are active and are controlled by ce# and oe#. on the other hand, if the byte# pin is set at logic 0, then the device is in byte configuration, and only data i/o pins dq0-dq7 are active and controlled by ce# and oe#. the data i/o pins dq8-dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. standby mode the en29f800 has a cmos-compatible standby mode, which reduces the current to < 1a (typical). it is placed in cmos-compatible standby when the ce pin is at v cc 0.5. reset# and byte# pin must also be at cmos input levels. the device also has a ttl-compatible standby mode, which reduces the maximum v cc current to < 1ma. it is placed in ttl-compatible standby when the ce pin is at v ih . when in standby modes, the outputs are in a high-impedance state independent of the oe input. read mode the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume commands for more additional information. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see the reset command additional details. output disable mode when the ce or oe pin is at a logic high level (v ih ), the output from the en29f800 is disabled. the output pins are placed in a high impedance state. auto select identification mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq15 Cdq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (10.5 v to 11.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in autoselect codes (high voltage method) table. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining address bits that are dont-care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq15Cdq0.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 8 en29f800 rev. e, issue date: 2001/07/05 to access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v id . see command definitions for details on using the autoselect mode. write mode programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. the command definitions in table 5 show the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using dq7 or dq6. see write operation status for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a 0 back to a 1. attempting to do so may halt the operation and set dq5 to 1, or cause the data# polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still 0. only erase operations can convert a 0 to a 1. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. sector protection/unprotection must be implemented using programming equipment. the procedure re- quires a high voltage (v id ) on address pin a9 and the control pins. details on this method are provided in a supplement, which can be obtained by contacting a representative of eon silicon devices, inc. temporary sector unprotect this feature allows temporary unprotection of previously protected sector groups to change data while in-system. the sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sector groups can be programmed or erased by simply selecting the sectgor addresses. once is removed from the reset# pin, all the previously protected sector are protected again. see accompanying figure and timing diagrams for more details. start reset#=v id (note 1) perform erase or program operations reset#=v ih temporary sector unprotect completed (note 2) notes: 1. all protected sectors unprotected. 2. previously protected sectors protected again.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 9 en29f800 rev. e, issue date: 2001/07/05 hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the command definitions table. additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during vcc power up and power down transitions, or from system noise. low v cc write inhibit when vcc is less than v lko , the device does not accept any write cycles. this protects data during vcc power up and power down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until vcc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when vcc is greater than v lko . write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce or we do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of ce = v ih , or we = v ih . to initiate a write cycle, ce and we must be a logical zero. if ce , we , and oe are all logical zero (not recommended usage), it will be considered a write. power-up write inhibit during power-up, the device automatically resets to read mode and locks out write cycles. even with ce = v il , we = v il and oe = v ih , the device will not accept commands on the rising edge of we .
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 10 en29f800 rev. e, issue date: 2001/07/05 command definitions the operations of the en29f800 are selected by one or more commands written into the command register to perform read/reset memory, read id, read sector protection, program, sector erase, chip erase, erase suspend and erase resume. commands are made up of data sequences written at specific addresses via the command register. the sequences for the specified operation are defined in the command definitions table (table 5). incorrect addresses, incorrect data values or improper sequences will reset the device to read mode. table 5. en29f800 command definitions bus cycles 1 st write cycle 2 nd write cycle 3 rd write cycle 4 th write cycle 5 th write cycle 6 th write cycle command sequence cycles add data add data add data add data add data add data read 1 ra rd reset 1 xxx f0 word 555 2aa 555 manufacturer id byte 4 aaa aa 555 55 aaa 90 000/ 100 7f/ 1c word 555 2aa 555 001/ 101 7f/ 2289 device id top boot byte 4 aaa aa 555 55 aaa 90 002/ 102 7f/ 89 word 555 2aa 555 001/ 101 7f/ 228a device id bottom boot byte 4 aaa aa 555 55 aaa 90 002/ 102 7f/ 8a xx00 word 555 2aa 555 (sa) x02 xx01 00 autoselect sector protect verify byte 4 aaa aa 555 55 aaa 90 (sa) x04 01 word 555 2aa 555 program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa 555 555 2aa 555 chip erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 word 555 2aa 555 555 2aa sector erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend 1 xxx b0 erase resume 1 xxx 30 address and data values indicated in hex ra = read address: address of the memory location to be read. this is a read cycle. rd = read data: data read from location ra during read operation. this is a read cycle. pa = program address: address of the memory location to be programmed. x = don t-care. pd = program data: data to be programmed at location pa sa = sector address: address of the sector to be erased or verified. address bits a18-a12 uniquely select any sector. reading array data the device is automatically set to reading array data after power up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. following an erase suspend command, erase suspend mode is entered. the system can read array data using the standard read timings, with the only difference in that if it reads at an address within erase suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. the reset command must be issued to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see next section for details on reset.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 11 en29f800 rev. e, issue date: 2001/07/05 reset command writing the reset command to the device resets the device to reading array data. address bits are dont- care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. this is an alternative method which is intended for prom programmers and requires v id on address bit a9. two unlock cycles followed by the autoselect command initiate the autoselect command sequence. autoselect mode is then entered and the system may read at any address any number of times, without needing another command sequence. the system must write the reset command to exit the autoselect mode and return to reading array data. word / byte programming command the device may be programmed by byte or by word, depending on the state of the byte# pin. programming the en29f800 is performed by using a four bus-cycle operation (two unlock write cycles followed by the program setup command and program data write cycle). when the program command is executed, no additional cpu controls or timings are necessary. an internal timer terminates the program operation automatically. address is latched on the falling edge of ce or we , whichever is last; data is latched on the rising edge of ce or we , whichever is first. programming status may be checked by sampling data on dq7 ( data polling) or on dq6 (toggle bit). when the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. note that data can not be programmed from a 0 to a 1. only an erase operation can change a data from 0 to 1. when programming time limit is exceeded, dq5 will produce a logical 1 and a reset command can return the device to read mode. chip erase command chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 12 en29f800 rev. e, issue date: 2001/07/05 any commands written to the chip during the embedded chip erase algorithm are ignored. the system can determine the status of the erase operati on by using dq7, dq6, or dq2. see write operation status for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. flowchart 4 illustrates the algorithm for the erase operation. see the erase/program operations tables in ac characteristics for parameters, and to the chip/sector erase operation timings for timing waveforms. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to write operation status for information on these status bits. flowchart 4 illustrates the algorithm for the erase operation. refer to the erase/program operations tables in the ac characteristics section for parameters, and to the sector erase operations timing diagram for timing waveforms. erase suspend / resume command the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. addresses are dont-cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase- suspended sectors produces status data on dq7Cdq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see write operation status for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status for more information. the autoselect command is not supported during erase suspend mode. the system must write the erase resume command (address bits are dont-care) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 13 en29f800 rev. e, issue date: 2001/07/05 write operation status dq7 dat a polling the en29f800 provides data polling on dq7 to indicate to the host system the status of the embedded operations. the data polling feature is active during the byte programming, sector erase, chip erase, erase suspend. (see table 6) when the byte programming is in progress, an attempt to read the device will produce the complement of the data last written to dq7. upon the completion of the byte programming, an attempt to read the device will produce the true data last written to dq7. for the byte programming, data polling is valid after the rising edge of the fourth we or ce pulse in the four-cycle sequence. when the embedded erase is in progress, an attempt to read the device will produce a 0 at the dq7 output. upon the completion of the embedded erase, the device will produce the 1 at the dq7 output during the read. for chip erase, the data polling is valid after the rising edge of the sixth we or ce pulse in the six-cycle sequence. for sector erase, data polling is valid after the last rising edge of the sector erase we or ce pulse. data polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. otherwise, data polling may give an inaccurate result if the address used is in a protected sector. just prior to the completion of the embedded operations, dq7 may change asynchronously when the output enable ( oe ) is low. this means that the device is driving status information on dq7 at one instant of time and valid data at the next instant of time. depending on when the system samples the dq7 output, it may read the status of valid data. even if the device has completed the embedded operations and dq7 has a valid data, the data output on dq0-dq6 may be still invalid. the valid data on dq0-dq7 will be read on the subsequent read attempts. the flowchart for data polling (dq7) is shown on flowchart 5. the data polling (dq7) timing diagram is shown in figure 8. ry/by: ready/busy the ry/by is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by status is valid after the rising edge of the final we pulse in the command sequence. since ry/by is an open-drain output, several ry/by pins can be tied together in parallel with a pull-up resistor to vcc. in the output is low, signifying busy, the device is actively erasing or programming. this includes programming in the erase suspend mode. if the output is high, signifying the ready, the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. dq6 toggle bit i the en29f800 provides a toggle bit on dq6 to indicate to the host system the status of the embedded programming and erase operations. (see table 6) during an embedded program or erase operation, successive attempts to read data from the device at any address (by toggling oe or ce ) will result in dq6 toggling between zero and one. once the embedded program or erase operation is complete, dq6 will stop toggling and valid data will be
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 14 en29f800 rev. e, issue date: 2001/07/05 read on the next successive attempts. during byte programming, the toggle bit is valid after the rising edge of the fourth we pulse in the four-cycle sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth-cycle sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erase we pulse. in byte programming, if the sector being written to is protected, dq6 will toggles for about 2 m s, then stop toggling without the data in the sector having changed. in sector erase or chip erase, if all selected blocks are protected, dq6 will toggle for about 100 m s. the chip will then return to the read mode without changing data in all protected blocks. toggling either ce or oe will cause dq6 to toggle. the flowchart for the toggle bit (dq6) is shown in flowchart 6. the toggle bit timing diagram is shown in figure 9 . dq5 exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1. this is a failure condition that indicates the program or erase cycle was not successfully completed. since it is possible that dq5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the dq6 is toggling after detecting a 1 on dq5. the dq5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a 1. under both these conditions, the system must issue the reset command to return the device to reading array data. dq3 sector erase timer after writing a sector erase command sequence, the output on dq3 can be used to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) when sector erase starts, dq3 switches from 0 to 1. this device does not support multiple sector erase command sequences so it is not very meaningful since it immediately shows as a 1 after the first 30h command. future devices may support this feature. dq2 erase toggle bit ii the toggle bit on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era-sure. thus, both status bits are required for sector and mode information. refer to table 5 to compare outputs for dq2 and dq6. flowchart 6 shows the toggle bit algorithm, and the section dq2: toggle bit explains the algorithm. see also the dq6: toggle bit i subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the dq2 vs. dq6 figure shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to flowchart 6 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7Cdq0 at least twice in a row to determine whether a toggle bit is toggling.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 15 en29f800 rev. e, issue date: 2001/07/05 typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7 Cdq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of flowchart 6). write operation status operation dq7 dq6 dq5 dq3 dq2 ry/by # embedded program algorithm dq7# toggle 0 n/a no toggle 0 standard mode embedded erase algorithm 0 toggle 0 1 toggle 0 reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase suspend mode erase-suspend program dq7# toggle 0 n/a n/a 0
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 16 en29f800 rev. e, issue date: 2001/07/05 table 6. status register bits dq name logic level definition 1 erase complete or erase sector in erase suspend 0 erase on-going dq7 program complete or data of non-erase sector during erase suspend 7 data polling dq7 program on-going -1-0-1-0-1-0-1- erase or program on-going dq6 read during erase suspend 6 toggle bit -1-1-1-1-1-1-1- erase complete 1 program or erase error 5 error bit 0 program or erase on-going 1 erase operation start 3 erase time bit 0 erase timeout period on-going -1-0-1-0-1-0-1- chip erase, erase or erase suspend on currently addressed sector. (when dq5=1, erase error due to currently addressed sector. program during erase suspend on- going at current address 2 toggle bit dq2 erase suspend read on non erase suspend sector notes: dq7 data polling: indicates the p/e c status check during program or erase, and on completion before checking bits dq5 for program or erase success. dq6 toggle bit: remains at constant level when p/e operations are complete or erase suspend is acknowledged. successive reads output complementary data on dq6 while programming or erase operation are on-going. dq5 error bit: set to 1 if failure in programming or erase dq3 sector erase command timeout bit: operation has started. only possible command is erase suspend (es). dq2 toggle bit: indicates the erase status and allows identification of the erased sector.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 17 en29f800 rev. e, issue date: 2001/07/05 embedded algorithms flowchart 1. embedded program start write program command sequence (shown below) data poll device last address? programming done increment address no yes verify data? flowchart 2. embedded program command sequence see the command definitions section for more information. 2aah / 55h 555h / aah 555h / a0h program address / program data
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 18 en29f800 rev. e, issue date: 2001/07/05 flowchart 3. embedded erase start write erase command sequence data poll from system or toggle bit successfully completed erase done data =ffh? yes no
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 19 en29f800 rev. e, issue date: 2001/07/05 flowchart 4. embedded erase command sequence see the command definitions section for more information. chip erase sector erase 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 555h/aah 2aah/55h 555h/80h 555h/aah 2aah/55h sector address/30h
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 20 en29f800 rev. e, issue date: 2001/07/05 flowchart 5. dat a polling algorithm flowchart 6. toggle bit algorithm no yes dq6 = toggle? dq5 = 1? dq6 = toggle? no no yes yes read data start read data fail pass no no dq7 = data? dq5 = 1? dq7 = data? yes yes no yes read data start read data fail pass
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 21 en29f800 rev. e, issue date: 2001/07/05 table 7. dc characteristics (t a = 0c to 70c or - 40c to 85c; v cc = 5.0v 10%) notes: (1) byte# and reset# pin input buffers are always enabled so that they draw power if not at full cmos supply voltages symbol parameter test conditions min typ max unit i li input leakage current 0v v in vcc 5 a i lo output leakage current 0v v out vcc 5 a supply current (read) ttl 19 30 ma (read) cmos byte 20 40 ma i cc1 (read) cmos word ce# = v il ; oe# = v ih ; f = 5mhz 28 50 ma supply current (standby - ttl) ce# = v ih 0.4 1.0 ma i cc2 (standby - cmos) (1) byte# = reset# = ce# = vcc 0.2v 0.3 5.0 a i cc3 supply current (program or erase) byte program, sector or chip erase in progress 30 60 ma v il input low voltage -0.5 0.8 v v ih input high voltage 2 vcc 0.5 v v ol output low voltage i ol = 2 ma 0.45 v output high voltage ttl i oh = -2.5 ma 2.4 v v oh output high voltage cmos i oh = -100 a vcc - 0.4v v v id a9 voltage (electronic signature) 10.5 11.5 v i id a9 current (electronic signature) a9 = v id 100 a v lko supply voltage (erase and program lock-out) 3.2 4.2 v
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 22 en29f800 rev. e, issue date: 2001/07/05 test conditions test specifications test conditions -45 -55 -70 -90 unit output load 1 ttl gate output load capacitance, c l 30 30 100 100 pf input rise and fall times 5 5 20 20 ns input pulse levels 0.0-0.3 0.0-0.3 0.45-2.4 0.45-2.4 v input timing measurement reference levels 1.5 1.5 0.8, 2.0 0.8, 2.0 v output timing measurement reference levels 1.5 1.5 0.8, 2.0 0.8, 2.0 v device under test c l 6.2 k w 2.7 k w 5.0 v note: diodes are in3064 or equivalent
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 23 en29f800 rev. e, issue date: 2001/07/05 ac characteristics hardware reset (reset#) speed options parameter std description test setup -45 -55 -70 -90 unit t ready reset# pin low to read or write embedded algorithms max 20 m s t ready reset# pin low to read or write non embedded algorithms max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read min 50 ns reset# timings t rh t rp t ready 0 v ry/by# ce# oe# reset# reset timings not during automatic algorithms t ready t rh t rp ry/by# ce# oe# reset# reset timings during automatic algorithms
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 24 en29f800 rev. e, issue date: 2001/07/05 ac characteristics word / byte configuration (byte#) speed std parameter description -45 -55 -70 -90 -120 unit t elfl /t elfh ce# to byte# switching low or high max 0 0 0 0 0 ns t flqz byte# switching low to output high z max 20 20 20 20 30 ns t fhqv byte# switching high to output active min 45 55 70 90 120 ns byte timings for read operations byte timings for read operations address input dq15 output data output (dq0-dq7) data output (dq0-dq14) address input dq15 output data output (dq0-dq7) data output (dq0-dq14) t elfl t elfh t flqz t fhqv ce oe byte dq0-dq14 dq15 / a-1 byte dq0-dq14 dq15 / a-1 switching from word to byte mode switching from byte to word mode t set t hold the falling edge of the last we signal ce we byte
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 25 en29f800 rev. e, issue date: 2001/07/05 table 8. ac characteristics read-only operations characteristics parameter symbols speed options jedec standard description test setup -45 -55 -70 -90 unit t avav t rc read cycle time min 45 55 70 90 ns t avqv t acc address to output delay ce = v il oe = v il max 45 55 70 90 ns t elqv t ce chip enable to output delay oe = v il max 45 55 70 90 ns t glqv t oe output enable to output delay max 25 30 30 35 ns t ehqz t df chip enable to output high z max 20 20 20 20 ns t ghqz t df output enable to output high z max 20 20 20 20 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min 0 0 0 0 ns notes: for - 50 vcc = 5.0v 5% output load : 1 ttl gate and 30pf input rise and fall times: 5ns input rise levels: 0.0 v to 3.0 v timing measurement reference level, input and output: 1.5 v for all others: vcc = 5.0v 10% output load: 1 ttl gate and 100 pf input rise and fall times: 20 ns input pulse levels: 0.45 v to 2.4 v timing measurement reference level, input and output: 0.8 v and 2.0 v figure 5. ac waveforms for read operations addresses ce# oe# we# outputs reset# ry/by# 0v output valid t rc t acc t oe t ce t oeh t oh t df high z addresses stable
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 26 en29f800 rev. e, issue date: 2001/07/05 table 9. ac characteristics write (erase/program) operations parameter symbols speed options jedec standard description -45 -55 -70 -90 unit t avav t wc write cycle time min 45 55 70 90 ns t avwl t as address setup time min 0 0 0 0 ns t wlax t ah address hold time min 35 45 45 45 ns t dvwh t ds data setup time min 20 25 30 45 ns t whdx t dh data hold time min 0 0 0 0 ns t oes output enable setup time min 0 0 0 0 ns read min 0 0 0 0 ns t oeh output enable hold time toggle and data polling min 10 10 10 10 ns t ghwl t ghwl read recovery time before write ( oe high to we low) min 0 0 0 0 ns t elwl t cs ce setuptime min 0 0 0 0 ns t wheh t ch ce hold time min 0 0 0 0 ns t wlwh t wp write pulse width min 25 30 35 45 ns t whdl t wph write pulse width high min 20 20 20 20 ns t whwh1 t whwh1 programming operation (word and byte mode) typ 7 7 7 7 s max 200 200 200 200 s t whwh2 t whwh2 sector erase operation typ 0.3 0.3 0.3 0.3 s max 5 5 5 5 s t whwh3 t whwh3 chip erase operation typ 3 3 3 3 s max 35 35 35 35 s t vcs vcc setup time min 50 50 50 50 s t vidr rise time to v id min 500 500 500 500 ns
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 27 en29f800 rev. e, issue date: 2001/07/05 table 10. ac characteristics write (erase/program) operations alternate ce controlled writes parameter symbols speed options jedec standard description -45 -55 -70 -90 unit t avav t wc write cycle time min 45 55 70 90 ns t avel t as address setup time min 0 0 0 0 ns t elax t ah address hold time min 35 45 45 45 ns t dveh t ds data setup time min 20 25 30 45 ns t ehdx t dh data hold time min 0 0 0 0 ns t oes output enable setup time min 0 0 0 0 ns t oeh output enable read 0 0 0 0 0 ns hold time toggle and data polling 10 10 10 10 10 ns t ghel t ghel read recovery time before write ( oe high to ce low) min 0 0 0 0 ns t wlel t ws we setuptime min 0 0 0 0 ns t ehwh t wh we hold time min 0 0 0 0 ns t eleh t cp write pulse width min 25 30 35 45 ns t ehel t cph write pulse width high min 20 20 20 20 ns t whwh1 t whwh1 programming operation (byte and word mode) typ 7 7 7 7 s max 200 200 200 200 s t whwh2 t whwh2 sector erase operation typ 0.3 0.3 0.3 0.3 s max 5 5 5 5 s t whwh3 t whwh3 chip erase operation typ 3 3 3 3 s max 35 35 35 35 s t vcs vcc setup time min 50 50 50 50 s t vidr rise time to v id min 500 500 500 500 ns
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 28 en29f800 rev. e, issue date: 2001/07/05 table 11. erase and programming performance limits parameter typ max unit comments sector erase time 1 8 sec chip erase time 19 35 sec excludes 00h programming prior to erasure byte programming time 7 300 s word programming time 7 300 s byte 8.2 24.5 chip programming time word 4.1 12.2 sec excludes system level overhead erase/program endurance 100k cycles minimum 100k cycles guaranteed table 12. latch up characteristics parameter description min max input voltage with respect to v ss on all pins except i/o pins (including a9, reset and oe ) -1.0 v 12.0 v input voltage with respect to v ss on all i/o pins -1.0 v vcc + 1.0 v vcc current -100 ma 100 ma note : these are latch up characteristics and the device should never be put under these conditions. refer to absolute maximum ratings for the actual operating limits. table 14. 32-pin tsop pin capa citance @ 25c, 1.0mhz parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf table 15. data retention parameter description test conditions min unit 150c 10 years minimum pattern data retention time 125c 20 years
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 29 en29f800 rev. e, issue date: 2001/07/05 switching waveforms figure 6. ac waveforms for chip/sector erase operations timings notes: 1. sa=sector address (for sector erase), va=valid address for reading status, d out =true data at read address. 2. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. t dh t ds t busy t wph t ch t wp t cs t vcs t rb t wc t as t ah t ghwl t whwh2 or t whwh3 0x2aa sa va va 0x55 0x30 status d out addresses ce# oe# we# data ry/by# v cc 0x555 for chip erase 0x555 for chip erase erase command sequence (last 2 cycles) read status data (last two cycles)
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 30 en29f800 rev. e, issue date: 2001/07/05 figure 7. program operation timings notes: 1. pa=program address, pd=program data, d out is the true data at the program address. 2. v cc shown in order to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. t vcs t dh t rb t whwh1 t busy t ds t cs t wph t ch t wp t ghwl t wc t as t ah 0x555 pa pa pa pd status d out oxa0 addresses ce# oe# we# data ry/by# v cc program command sequence (last 2 cycles) program command sequence (last 2 cycles)
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 31 en29f800 rev. e, issue date: 2001/07/05 figure 8. ac waveforms for /data polling during embedded algorithm operations notes: 1. va=valid address for reading data# polling status data 2. this diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cy cle. figure 9. ac waveforms for toggle bit during embedded algorithm operations t oeh t df t oh t busy t oe complement status data comple- ment true true status data valid data valid data t ce t acc t ch t rc va va va addresses ce# oe# we# dq[7] dq[6:0] ry/by# t rc t acc t ce t oe t oeh t ch t df t oh t busy va va va va valid status valid status valid status valid data (first read) (second read) (stops toggling) addresses ce# oe# we# dq6, dq2 ry/by#
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 32 en29f800 rev. e, issue date: 2001/07/05 ac characteristics dq2 vs. dq6 temporary sector unprotect speed option parameter std description -45 -55 -70 -90 unit t vidr v id rise and fall time min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s temporary sector unprotect timing diagram reset# 0 or 5 v t vidr t vidr t rsp v id 0 or 5v ce# we# ry/by# we# dq6 dq2 enter embedded erase erase suspend enter erase suspend program erase resume erase enter suspend read enter suspend program erase erase complete erase suspend read
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 33 en29f800 rev. e, issue date: 2001/07/05 figure 10. alternate ce# controlled write operation timings notes: pa = address of the memory location to be programmed. pd = data to be programmed at byte address. va = valid address for reading program or erase status d out = array data read at va shown above are the last two cycles of the program or erase command sequence and the last staus read cycle reset# shown to illustrate t rh measurement references. it cannot occur as shown during a valid command sequence. t wc t rh t as t ah t wh t ghel t cph t cp t ws t dh t ds t busy t cwhwh1 / t cwhwh2 / t cwhwh3 status d out 0xa0 for program 0x55 for erase pd for program 0x30 for sector erase 0x10 for chip erase va addresses we# oe# ce# data ry/by# reset# pa for program sa for sector erase 0x555 for chip erase 0x555 for program 0x2aa for erase
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 34 en29f800 rev. e, issue date: 2001/07/05 figure 4. tsop
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 35 en29f800 rev. e, issue date: 2001/07/05
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 36 en29f800 rev. e, issue date: 2001/07/05 absolute maximum ratings parameter value unit storage temperature -65 to +125 c plastic packages -65 to +125 c ambient temperature with power applied -55 to +125 c output short circuit current 1 200 ma a9, oe#, reset# 2 -0.5 to +11.5 v all other pins 3 -0.5 to vcc+0.5 v voltage with respect to ground vcc -0.5 to +7.0 v notes: 1. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. 2. minimum dc input voltage on a9, oe#, reset# pins is C0.5v. during voltage transitions, a9, oe#, reset# pins may undershoot v ss to C1.0v for periods of up to 50ns and to C2.0v for periods of up to 20ns. see figure below. maximum dc input voltage on a9, oe#, and reset# is 11.5v which may overshoot to 12.5v for periods up to 20ns. 3. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, inputs may undershoot v ss to C1.0v for periods of up to 50ns and to C2.0 v for periods of up to 20ns. see figure below. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may overshoot to v cc + 2.0 v for periods up to 20ns. see figure below. 4. stresses above the values so mentioned above may cause permanent damage to the device. these values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. recommended operating ranges 1 parameter value unit ambient operating temperature commercial devices industrial devices 0 to 70 -40 to 85 c operating supply voltage vcc for 5% devices vcc for 10% devices 4.75 to 5.25 4.5 to 5.5 v 1. recommended operating ranges define those limits between which the functionality of the device is guaranteed. maximum negative overshoot maximum positive overshoot waveform waveform
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 37 en29f800 rev. e, issue date: 2001/07/05 ordering information en29f800 t 45 t i temperature range (blank) = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) package t = 48-pin tsop s = small outline package speed 45 = 45ns 55 = 55ns 70 = 70ns 90 = 90ns boot code sector architecture t = top sector b = bottom sector base part number en = eon silicon devices 29f = flash, 5v read program erase 800 = 8 megabit (1024k x 8 / 512 x 16)
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 38 en29f800 rev. e, issue date: 2001/07/05 revisions list a,b,c: preliminary d (2001.07.03): table 7. icc2 is with byte# and reset# pin at full cmos levels pg. 9 logical inhibit section now says that if ce , we , and oe are all logical zero (not recommended usage), it will be considered a write. vid is everywhere changed to be v id =11.5 0.5v e (2001.07.05): block changed to sector lacthup >= 200ma line removed from first page deleted sector un/protect flowcharts chip erase and sector erase command descriptions modified. dq7,dq5,dq3 status polling descriptions modified. table 12 latchup characteristics modified changed p/e endurance to 100k everywhere changed absolute maximum ratings

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